The present invention relates in general to digital video and audio, and more particularly to phase-locking a clock to a digital audio signal embedded within a digital video signal.
Audio data embedded within a digital video stream has a different integer frequency relationship to the video clock. For this reason, a conventional phase-locked loop locked to the video clock requires dividers for both the video clock signal and the synthesized audio clock signal as shown in FIG. 1. Depending upon the type of video signal, the audio signal's integer frequency relationship with the video clock may be relatively large. Conventionally, with some video signals, such as the National Television System Committee (NTSC) standard, the divider ratios become very large and impracticable to implement.
In the case of 14.31818 MHz NTSC D2 video, the integer ratio between the video clock and the 48 KHz audio clock is 4777500/16016. A conventional phase-locked loop that derives the 48 KHz audio signal in this case requires two dividers as shown in FIG. 1. One divides the video clock by 4777500, denoted by N in FIG. 1, and another which divides the audio clock by 16016, which is denoted by M FIG. 1. Also, in this case an additional problem is that the divided down frequency into the phase detector would be 2.997003 Hz, which requires a very slow loop filter.
Furthermore, accommodating a conventional multi-standard decoder requires switching divider ratios for each different video standard. For example, the divider ratio (M/N) described above for the NTSC D2 standard would change for both the Phase Alternate Line D2 (PAL D2) and 27 MHz D1 standards, which requires rather complex circuitry.
To avoid the above problems, another method to phase-lock a clock to an embedded digital audio signal is to detect each audio sample as it appears on the video and use that sample as an input to the phase detector of a phase-lock loop. This method is independent of the video standard, and works with a non-synchronous audio signal as well as with one synchronous to a video signal. However, significant problems with the above method exist. It happens that the audio data signal is "bursty" in that it has a great deal of phase jitter because the audio samples are dispersed very unevenly through the video signal. The phase jitter on the audio samples can be transferred to the regenerated audio clock created by the phase-lock loop and at times cause the phase detector to lose or gain cycles and not to function.
What is desired is a system for phase-locking a clock to a digital audio signal embedded within a digital video signal where phase jitter associated with the digital audio signal does not prevent the functionality of the phase-lock loop or have unacceptable effects on the generated audio clock signal.